The present invention is intended to prevent erroneous data writing of a multiport memory such as a so-called dual-port memory, etc. and enhance reliability of the data writing. The background of the advent of multiport memory will be explained first.
In a well known conventional semiconductor memory, an attempt to share the processing with each CPU by connecting a pair of CPUs to only one semiconductor memory requires connection between each CPU and only one semiconductor memory with a data bus line for sending or receiving information. However, if the data bus line is used in common from a plurality of CPUs, while one CPU sends or receives data from a semiconductor memory, the other CPU naturally cannot send or receive data from this semiconductor memory. Therefore, even when a plurality of CPUs are connected to an ordinary semiconductor memory, it has never been possible to simultaneously connect or allow access by a plurality of CPUs to the semiconductor memory for simultaneous data sending and receiving.
A multiport memory to which the present invention is applied enables such simultaneous data sending and receiving to a plurality of CPUs which cannot be realized with a conventional semiconductor memory. Namely, a multiport memory has a plurality of ports for only one memory cell array and connect CPUs to respective ports in order to enable the shared processing by each CPU. A multiport memory in which a total of two ports, one on the left side of memory cell array and one on the right side thereof, are provided is particularly called a dual-port memory which is used most frequently.